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1 high voltage synchronous rectified buck mosfet drivers isl6208, iSL6208B the isl6208 and iSL6208B are high frequency, dual mosfet drivers, optimized to drive two n-channel power mosfets in a synchronous-rectified buck converter topology. they are especially suited for mobile computing applications that require high efficiency and excellent thermal performance. these drivers, combined with an intersil multiphase buck pwm controller, form a complete single-stage core-voltage regulator solution for advanced mobile microprocessors. isl6208 and iSL6208B have the same function but different packages. the descriptions in this datasheet are based on isl6208 and also apply to iSL6208B. the isl6208 features 4a typical sinking current for the lower gate driver. this current is capable of holding the lower mosfet gate off during the rising edge of the phase node. this prevents shoot-through power loss caused by the high dv/dt of phase voltages. the operating voltage matches the 30v breakdown voltage of the mosfet s commonly used in mobile computer power supplies. the isl6208 also features a three-state pwm input that, working together with intersil?s multiphase pwm controllers, will prevent negative voltage output during cpu shutdown. this feature eliminates a protective schottky diode usually seen in a microprocessor power systems. mosfet gates can be efficiently switched up to 2mhz using the isl6208. each driver is capable of driving a 3000pf load with propagation delays of 8n s and transition times under 10ns. bootstrapping is implemented with an internal schottky diode. this reduces system cost and complexity, while allowing the use of higher performance mosfets. adaptive shoot- through protection is integrated to prevent both mosfets from conducting simultaneously. a diode emulation feat ure is integrated in the isl6208 to enhance converter efficiency at light load conditions. this feature also allows for monotonic start-up into pre-biased outputs. when diode emulation is enabled, the driver will allow discontinuous conduction mode by detecting when the inductor current reaches zero and subsequently turning off the low side mosfet gate. features ? dual mosfet drives for synchronous rectified bridge ? adaptive shoot-through protection ?0.5 on-resistance and 4a sink current capability ? supports high switching frequency up to 2mhz - fast output rise and fall time - low propagation delay ? three-state pwm input for power stage shutdown ? internal bootstrap schottky diode ? low bias supply current (5v, 80a) ? diode emulation for enhanced light load efficiency and pre-biased start-up applications ? vcc por (power-on-reset) feature integrated ? low three-state shutdown holdoff time (typical 160ns) ? pin-to-pin compatible with isl6207 ? qfn and dfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline dfn - dual flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile ? pb-free (rohs compliant) applications ? core voltage supplies for intel? and amd? mobile microprocessors ? high frequency low profile dc/dc converters ? high current low output voltage dc/dc converters ? high input voltage dc/dc converters related literature ?technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? ?technical brief tb389 ?pcb land pattern design and surface mount guidelines for mlfp packages? ?technical brief tb447 ?guidelines for preventing boot-to-phase stress on half-bridge mosfet driver ics? caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2004-2008, 2011, 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. january 31, 2012 fn9115.6
isl6208, iSL6208B 2 fn9115.6 january 31, 2012 pin configuration s block diagram ti ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl6208cbz isl62 08cbz -10 to +100 8 ld soic m8.15 isl6208crz 208z -10 to +100 8 ld 3x3 qfn l8.3x3 iSL6208Bcrz 8bc -10 to +100 8 ld 2x2 dfn l8.2x2d isl6208ibz isl62 08ibz -40 to +100 8 ld soic m8.15 isl6208irz 8irz -40 to +100 8 ld 3x3 qfn l8.3x3 iSL6208Birz 8bi -40 to +100 8 ld 2x2 dfn l8.2x2d notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs complian t and compatible with both snpb and pb-free soldering operation s). intersil pb-free products are msl classified at pb-free peak reflow temperatures th at meet or exceed the pb-free requirements of ipc/jedec j std -020. 3. for moisture sensitivity level (msl), please see device information page for isl6208 , iSL6208B . for more information on msl please see techbrief tb363 . isl6208cbz, isl6208ibz (8 ld soic) top view isl6208crz, isl6208irz (8 ld 3x3 qfn) top view iSL6208Bcrz, iSL6208Birz (8 ld 2x2 dfn) top view ugate boot pwm gnd 1 2 3 4 8 7 6 5 phase fccm vcc lgate 7 ugate phase 8 4 3 1 2 6 gnd lgate fccm vcc boot pwm 5 6 1 6 vcc lgate pwm gnd 5 6 6 phase fccm 7 8 ugate boot 2 3 4 vcc pwm 10k control logic shoot- through protection boot ugate phase lgate gnd vcc fccm thermal pad (for qfn and dfn package only) figure 1. block diagram
isl6208, iSL6208B 3 fn9115.6 january 31, 2012 ti absolute maximum rating s thermal information supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 7v input voltage (v fccm , v pwm ) . . . . . . . . . . . . . . . . . . . . -0.3v to vcc + 0.3v boot voltage (v boot-gnd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 33v boot to phase voltage (v boot-phase ). . . . . . . . . . . . . . . . -0.3v to 7v (dc) -0.3v to 9v (<10ns) phase voltage (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 30v gnd - 8v (<20ns pulse width, 10j) ugate voltage. . . . . . . . . . . . . . . . . . . . . . . . . . v phase - 0.3v (dc) to v boot v phase - 5v (<20ns pulse width, 10j) to v boot lgate voltage . . . . . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v (dc) to vcc + 0.3v gnd - 2.5v (<20ns pulse width, 5j) to vcc + 0.3v ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c thermal resistance (typical) ja (c/w) jc (c/w) 8 ld soic package (notes 5, 8) . . . . . . . . . 110 67 8 ld 3x3 qfn package (notes 6, 7) . . . . . . 80 15 8 ld 2x2 dfn package (notes 6, 7) . . . . . . 89 24 maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c maximum operating junction temperature . . . . . . . . . . . . . . . . . . +125c supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. the phase voltage is capable of withstan ding -7v when the boot pin is at gnd. 5. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 6. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 7. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 8. for jc , the ?case temp? location is taken at the package top center. electrical specifications recommended operating conditions, unless otherwise noted. boldface limits apply over the operating temperature range. parameter symbol test conditions min (note 10) typ max (note 10) units v cc supply current bias supply current i vcc pwm pin floating, v fccm = 5v - 80 - a por v cc rising -3.40 3.90 v v cc falling 2.40 2.90 - v hysteresis - 500 - mv bootstrap diode forward voltage v f v vcc = 5v, forward bias current = 2ma 0.50 0.55 0.65 v pwm input input current i pwm v pwm = 5v - 250 - a v pwm = 0v - -250 - a pwm three-state rising threshold v vcc = 5v 0.70 1.00 1.30 v pwm three-state falling threshold v vcc = 5v 3.5 3.8 4.1 v three-state shutdown hold-off time t tsshd v vcc = 5v, temperature = +25c 100 175 250 ns fccm input fccm low threshold 0.50 --v fccm high threshold -- 2.0 v switching time ugate rise time (note 9) t ru v vcc = 5v, 3nf load - 8.0 - ns lgate rise time (note 9) t rl v vcc = 5v, 3nf load - 8.0 - ns
isl6208, iSL6208B 4 fn9115.6 january 31, 2012 ugate fall time (note 9) t fu v vcc = 5v, 3nf load - 8.0 - ns lgate fall time (note 9) t fl v vcc = 5v, 3nf load - 4.0 - ns ugate turn-off propagation delay t pdlu v vcc = 5v, outputs unloaded - 18 - ns lgate turn-off propagation delay t pdll v vcc = 5v, outputs unloaded - 25 - ns ugate turn-on propagation delay t pdhu v vcc = 5v, outputs unloaded 10 20 30 ns lgate turn-on propagation delay t pdhl v vcc = 5v, outputs unloaded 10 20 30 ns ug/lg three-state propagation delay t pts v vcc = 5v, outputs unloaded - 35 - ns minimum lg on-time in dcm (note9) t lgmin - 400 - ns output upper drive source resistance r u 500ma source current - 1 2.5 upper driver source current (note 9) i u v ugate-phase = 2.5v - 2.00 - a upper drive sink resistance r u 500ma sink current - 1 2.5 upper driver sink current (note 9) i u v ugate-phase = 2.5v - 2.00 - a lower drive source resistance r l 500ma source current - 1 2.5 lower driver source current (note 9) i l v lgate = 2.5v - 2.00 - a lower drive sink resistance r l 500ma sink current - 0.5 1.0 lower driver sink current (note 9) i l v lgate = 2.5v - 4.00 - a notes: 9. limits established by characteriza tion and are not production tested. 10. parameters with min and/or max limits ar e 100% tested at +25c, unless otherwise sp ecified. temperature limits established b y characterization and are not production tested. electrical specifications recommended operating conditions, unless otherwise noted. boldface limits apply over the operating temperature range. parameter symbol test conditions min (note 10) typ max (note 10) units
isl6208, iSL6208B 5 fn9115.6 january 31, 2012 typical application with 2-phase converter +5v boot ugate phase lgate pwm fccm vcc drive v bat +5v boot ugate phase lgate pwm v bat +v core pgood vid fs gnd isen2 isen1 pwm2 pwm1 vsen main fb vcc +5v comp isl6208 control vcc drive isl6208 +5v dacout fccm fccm thermal pad thermal pad
isl6208, iSL6208B 6 fn9115.6 january 31, 2012 timing diagram functional pin description ugate the ugate pin is the upper gate drive output. connect to the gate of high-side power n-channel mosfet. boot boot is the floating bootstrap supply pin for the upper gate drive. connect the bootstrap capacitor between this pin and the phase pin. the bootstrap capacitor provides the charge to turn on the upper mosfet. see ?internal bootstrap diode? on page 8 for guidance in choosing the appropriate capacitor value. pwm the pwm signal is the control inpu t for the driver. the pwm signal can enter three distinct states during operation. see ?three-state pwm input? on page 8 for further details. connect this pin to the pwm output of the controller. gnd gnd is the ground pin for the ic. lgate lgate is the lower gate drive output. connect to gate of the low-side power n-channel mosfet. vcc connect the vcc pin to a +5v bias supply. place a high quality bypass capacitor from this pin to gnd. fccm the fccm pin enables or disa bles diode emulation. when fccm is low, diode emulation is allowed. otherwise, continuous conduction mode is forced. see ?diode emulation? on page 8 for more detail. phase connect the phase pin to the so urce of the upper mosfet and the drain of the lower mosfet. this pin provides a return path for the upper gate driver. description theory of operation designed for speed, the isl6208 dual mosfet driver controls both high-side and low-side n-channel fets from one externally provided pwm signal. a rising edge on pwm initiates th e turn-off of the lower mosfet (see ?timing diagram? above). after a short propagation delay [t pdll ], the lower gate begins to fall. typical fall times [t fl ] are provided in the ?electrical specifications? section. adaptive shoot- through circuitry monitors the lgate voltage. when lgate has fallen below 1v, ugate is allowed to turn on. this prevents both the lower and upper mosfets from conducting simultaneously, or shoot-through. a falling transition on pwm indicates the turn-off of the upper mosfet and the turn-on of the lower mosfet. a short propagation delay [t pdlu ] is encountered before the upper gate begins to fall [t fu ]. the upper mosfet gate -to-source voltage is monitored, and the lower gate is allowed to rise after the upper mosfet gate-to-source voltage drops below 1v. the lower gate then rises [t rl ], turning on the lower mosfet. this driver is optimized for converters with large step-down compared to the upper mosfet because the lower mosfet conducts for a much longer time in a switching period. the lower gate driver is therefore sized much larger to meet this application requirement. the 0.5 on-resistance and 4a sink current capability enable the lower gate driver to absorb the current injected to the lower gate through the drain-to-gate capacitor of the lower mosfet and prevent a shoot-through caused by the high dv/dt of the phase node. pwm ugate lgate t pdll t fl t pdhu t ru t pdlu t fu t pdhl t rl 1v 2.5v t ru t fu t fl 1v t pts t tsshd t tsshd t pts
isl6208, iSL6208B 7 fn9115.6 january 31, 2012 typical performance waveforms figure 2. load transient (0 - 30a, 3-phase) figure 3. load transient (30 - 0a, 3-phase) figure 4. dcm to ccm transition at no load figure 5. ccm to dcm transition at no load figure 6. pre-biased start-up in ccm mode figure 7. pre-biased start-up in dcm mode
isl6208, iSL6208B 8 fn9115.6 january 31, 2012 diode emulation diode emulation allows for higher converter efficiency under light load situations. with diode emulation active, the isl6208 will detect the zero current cro ssing of the output inductor and turn off lgate. this ensures that discontinuous conduction mode (dcm) is achieved. diode emulation is asynchronous to the pwm signal. therefore, the isl6208 will respond to the fccm input immediately after it changes state. refer to?typical performance waveforms? on page 7. note: intersil does not recommend diode emulation use with r ds(on) current sensing topologies. the turn-off of the low side mosfet can cause gross current measurement inaccuracies. three-state pwm input a unique feature of the isl6208 an d other intersil drivers is the addition of a shutdown window to the pwm input. if the pwm signal enters and remains within the shutdown window for a set holdoff time, the output drivers are disabled and both mosfet gates are pulled and held low. the shutdown state is removed when the pwm signal moves outside the shutdown window. otherwise, the pwm rising and falling thresholds outlined in the ?electrical specifications? table on page 3 determine when the lower and upper gates are enabled. adaptive shoot-through protection both drivers incorporate adaptive shoot-through protection to prevent upper and lower mosfets from conducting simultaneously and shorting the input supply. this is accomplished by ensuring the falling gate has turned off one mosfet before the other is allowed to turn on. during turn-off of the lower mosfet, the lgate voltage is monitored until it reaches a 1v threshold, at which time the ugate is released to rise. adaptive shoot-through circuitry monitors the upper mosfet gate-to-source voltage during ugate turn-off. once the upper mosfet gate-to-source voltage has dropped below a threshold of 1v, the lgate is allowed to rise. internal bootstrap diode this driver features an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstrap capacito r must have a maximum voltage rating above the maximum battery voltage plus 5v. the bootstrap capacitor can be chosen from equation 1: where q gate is the amount of gate charge required to fully charge the gate of the upper mosfet. the v boot term is defined as the allowable droop in the rail of the upper drive. as an example, suppose an up per mosfet has a gate charge, q gate , of 25nc at 5v and also assume the droop in the drive voltage over a pwm cycle is 200mv. one will find that a bootstrap capacitance of at least 0.125f is required. the next larger standard value capacitance is 0.15f. a good quality ceramic capacitor is recommended. power dissipation package power dissipation is mainly a function of the switching frequency and total gate charge of the selected mosfets. calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the ma ximum recommended operating junction temperature of +125c. the maximum allowable ic power dissipation for the so-8 package is approximately 800mw. when designing the driver into an application, it is recommended that the following calculation be performed to ensure safe operation at the de sired frequency for the selected mosfets. the power dissipated by the driver is approximated as shown in equation 2: where f sw is the switching frequency of the pwm signal. v u and v l represent the upper and lower gate rail voltage. q u and q l is the upper and lower gate charge determined by mosfet selection and any external capaci tance added to the gate pins. the lv cc v cc product is the quiescent power of the driver and is typically negligible. c boot q gate v boot -------------------- - (eq. 1) figure 8. bootstrap capa citance vs boot ripple voltage 20nc v boot_cap (v) c boot_cap (f) 2.0 1.6 1.4 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc 1.2 1.8 50n c pf sw 1.5v u q u v l q l + () i vcc v cc + = (eq. 2) figure 9. power dissipation vs frequency frequency (khz) 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 power (mw) q u = 50nc q l = 50nc q u = 50nc q l = 100nc q u =100nc q l = 200nc q u = 20nc q l =50nc
isl6208, iSL6208B 9 fn9115.6 january 31, 2012 layout considerations reducing phase ring the parasitic inductances of the pcb and power devices (both upper and lower fets) could cause increased phase ringing, which may lead to voltages that exceed the absolute maximum rating of the devices. when phase rings below ground, the negative voltage could add charge to the bootstra p capacitor through the internal bootstrap diode. under worst-case conditions, the added charge could overstress the boot and/or phase pins. to prevent this from happening, the user should perform a careful layout inspection to reduce trace inductances, and sele ct low lead inductance mosfets and drivers. d 2 pak and dpak packaged mosfets have high parasitic lead inductances, as opposed to soic-8. if higher inductance mosfets must be used, a schottky diode is recommended across the lower mosf et to clamp negative phase ring. a good layout would help reduce the ringing on the phase and gate nodes significantly: ? avoid using vias for decoupling components where possible, especially in the boot-to-phase path. little or no use of vias for vcc and gnd is also recommended. decoupling loops should be short. ? all power traces (ugate, phase, lgate, gnd, vcc) should be short and wide, and avoid using vias. if vias must be used, two or more vias per layer transition is recommended. ? keep the source of the upper fet as close as thermally possible to the drain of the lower fet. ? keep the connection in between the source of lower fet and power ground wide and short. ? input capacitors should be placed as close to the drain of the upper fet and the source of the lower fet as thermally possible. note: refer to intersil tech brief tb447 for more information. thermal management for maximum thermal performance in high current, high switching frequency applications , connecting the thermal pad of the qfn and dfn parts to the power ground with multiple vias, or placing a low noise copper plane underneath the soic part is recommended. this heat spreading allows the part to achieve its full thermal potential.
isl6208, iSL6208B 10 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn9115.6 january 31, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl6208 , iSL6208B to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change january 17, 2012 fn9115.6 added limits for ?ugate turn-on propagat ion delay? and ?lgate turn-on propagation delay? on page 4. october 26, 2011 fn9115.5 removed limits for ?ugate turn-on propagation delay? and ?lgate turn-on propagation delay? on page 4. july 12, 2011 fn9115.4 added ?revision history? on page 10 and ?products? on page 10. added iSL6208Bcrz and iSL6208Birz parts to ?ordering in formation? on page 2. removed leaded, obsolete devices (isl6208cb, isl6208cr, isl6208ib, isl6208ir). updated tape & reel note in ?ordering information? on page 2 from "add "-t" suffix for tape and reel." to new standard "add "-t*" suffix for tape and reel." th e "*" covers all possible tape and reel options added msl note to ?ordering information? on page 2 added pinout for iSL6208Birz and iSL6208Bcrz on page 2 added ?thermal information? on page 3 for new isl6802b package, 8 ld 2x2 dfn. added theta jc for soic package and note 8. removed "parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and ar e not production tested." from common conditions of spec table. added as note in min max co lumns of ?electrical specifications? table. added standard text "boldface limits apply over the oper ating temp range" to common conditions of spec table. bolded applicable specs. updated ?package outline drawing? on page 13 (m8.15) as follows: updated to new pod format by removing table and movi ng dimensions onto drawing and adding land pattern
isl6208, iSL6208B 11 fn9115.6 january 31, 2012 package outline drawing l8.3x3 8 lead quad flat no-lead plastic package rev 2, 3/07 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view bottom view side view (4x) 0.15 6 index area pin 1 3.00 b a 3.00 3 5 4 8x 0.60 0.15 2 c 8x 0.28 0.05 m 4 0.10 b a 0.65 4x 8 7 6 pin #1 index area 6 1 .10 0 . 15 1 0 . 90 0.1 see detail "x" base plane seating plane 0.10 0.08 c c c c 0 . 05 max. 0 . 2 ref 0 . 00 min. 5 ( 2. 60 typ ) ( 1. 10 ) ( 8x 0 . 80) ( 8x 0 . 28 ) ( 4x 0 . 65 )
isl6208, iSL6208B 12 fn9115.6 january 31, 2012 package outline drawing l8.2x2d 8 lead dual flat no-lead plastic package (dfn) with exposed pad rev 0, 3/11 bottom view detail "x" side view typical recommended land pattern top view pin #1 b 0.10 m a c c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. 0 . 05 max. 0 . 2 ref c index area pin 1 6 (4x) 0.15 a b 1 package 2.00 2.00 1.550.10 0.900.10 0.22 ( 6x0.50 ) ( 8x0.22 ) 2.00 2.00 ( 8x0.30 ) ( 8x0.20 ) ( 8x0.30 ) 0.50 8 0.90 1.55 6x 0.900.10 index area outline located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance: decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 6 4
isl6208, iSL6208B 13 fn9115.6 january 31, 2012 package outline drawing m8.15 8 lead narrow body small outline plastic package rev 3, 3/11 detail "a" top view index area 123 -c- seating plane x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m-1982. 2. package length does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. package width does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 5. terminal numbers are shown for reference only. 6. the lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. controlling dimension: millimeter. co nverted inch dimensions are not necessarily exact. 8. this outline conforms to jedec publication ms-012-aa issue c. side view ?a side view ?b? 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 8 0 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 1 2 3 4 5 6 7 8 typical recommended land pattern 2.20 (0.087) 0.60 (0.023)

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